ST STM32G471 User Manual

General-purpose timers (TIM15/TIM16/TIM17) RM0440
1436/2126 RM0440 Rev 4
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample tim_brk input and the length of the digital
filter applied to tim_brk. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: No filter, tim_brk acts asynchronously
0001: f
SAMPLING
=f
tim_ker_ck
, N=2
0010: f
SAMPLING
=f
tim_ker_ck
, N=4
0011: f
SAMPLING
=f
tim_ker_ck
, N=8
0100: f
SAMPLING
=f
DTS
/2, N=6
0101: f
SAMPLING
=f
DTS
/2, N=8
0110: f
SAMPLING
=f
DTS
/4, N=6
0111: f
SAMPLING
=f
DTS
/4, N=8
1000: f
SAMPLING
=f
DTS
/8, N=6
1001: f
SAMPLING
=f
DTS
/8, N=8
1010: f
SAMPLING
=f
DTS
/16, N=5
1011: f
SAMPLING
=f
DTS
/16, N=6
1100: f
SAMPLING
=f
DTS
/16, N=8
1101: f
SAMPLING
=f
DTS
/32, N=5
1110: f
SAMPLING
=f
DTS
/32, N=6
1111: f
SAMPLING
=f
DTS
/32, N=8
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0:tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI
bit.
1:tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E,
CC1NE in TIMx_CCER register)
See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx
capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1429).
Bit 14 AOE: Automatic output enable
0:MOE can be set only by software
1:MOE can be set by software or automatically at the next update event (if the tim_brk input
is not active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input tim_brk is active low
1: Break input tim_brk is active high
Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (tim_brk and tim_sys_brk event) disabled
1; Break inputs (tim_brk and tim_sys_brk event) enabled
Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English