RM0440 Rev 4 1437/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx
capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1429).
0:When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output
control which is taken over by the AFIO logic, which forces a Hi-Z state)
1:When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as
CC1E=1 or CC1NE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx
capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1429).
0:When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output
signal=0)
1:When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as
CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
dtg
with t
dtg
=t
DTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
dtg
with T
dtg
=2xt
DTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=8xt
DTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=16xt
DTS
Example if T
DTS
=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
To Next Page
Loading...
Need help?
General
