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RM0440 Rev 4 1565/2126

RM0440 Real-time clock (RTC)

1592

35.6.9 RTC calibration register (RTC_CALR)

This register is write protected. The write access procedure is described in RTC register

write protection on page 1547.

Address offset: 0x28

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: Write protection key

This byte is written by software.

Reading this byte always returns 0x00.

Refer to RTC register write protection for a description of how to unlock RTC register write

protection.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

CALP CALW8

CALW

Res. Res. Res. Res. CALM[8:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALP: Increase frequency of RTC by 488.5 ppm

0: No RTCCLK pulses are added.

1: One RTCCLK pulse is effectively inserted every 2

pulses (frequency increased by

488.5 ppm).

This feature is intended to be used in conjunction with CALM, which lowers the frequency of

the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of

RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) -

CALM.

Refer to Section 35.3.13: RTC smooth digital calibration.

Bit 14 CALW8: Use an 8-second calibration cycle period

When CALW8 is set to 1, the 8-second calibration cycle period is selected.

Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 35.3.13: RTC smooth

digital calibration.

ST STM32G471 User Manual

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