RM0440 Rev 4 1649/2126
RM0440 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1733
37.7.2 USART control register 1 [alternate] (USART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
FIFO
EN
M1 EOBIE RTOIE DEAT[4:0] DEDT[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15141312111098765 43210
OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 FIFOEN: FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE=0).
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit
M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit
M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit
This bit can only be written when the USART is disabled (UE=0).
Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate
(0x7F and 0x55 frames detection) are not supported.
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at
reset value. Refer to Section 37.4: USART implementation on page 1595.
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Section 37.4: USART implementation on page 1595.
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