RM0440 Rev 4 1659/2126
RM0440 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1733
Bit 12 OVRDIS: Overrun Disable
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new
data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is
written directly in USART_RDR register. Even when FIFO management is enabled, the
RXNE flag is to be used.
This bit can only be written when the USART is disabled (UE=0).
Note: This control bit enables checking the communication flow w/o reading the data
Bit 11 ONEBIT: One sample bit method enable
This bit enables the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NE) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE=0).
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 37.4: USART implementation on page 1595.
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0).
If the nCTS input is deasserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while nCTS is asserted,
the transmission is postponed until nCTS is asserted.
This bit can only be written when the USART is disabled (UE=0)
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 37.4: USART implementation on page 1595.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The nRTS output is asserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Refer to Section 37.4: USART implementation on page 1595.
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
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