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ST STM32G471 User Manual

ST STM32G471
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RM0440 Rev 4 1667/2126
RM0440 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1733
Bit 15 ABRF: Auto baud rate flag
This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set,
generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 13 UDR: SPI slave underrun error flag
In slave transmission mode, this flag is set when the first clock pulse for data transmission
appears while the software has not yet loaded any value into USART_TDR. This flag is
reset by setting UDRCF bit in the USART_ICR register.
0: No underrun error
1: underrun error
Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at
reset value. Refer to Section 37.4: USART implementation on page 1595.
Bit 12 EOBF: End of block flag
This bit is set by hardware when a complete block has been received (for example T=1
Smartcard mode). The detection is done when the number of received bytes (from the start
of the block, including the prologue) is equal or greater than BLEN + 4.
An interrupt is generated if the EOBIE=1 in the USART_CR2 register.
It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.
0: End of Block not reached
1: End of Block (number of characters) reached
Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer
to Section 37.4: USART implementation on page 1595.
Bit 11 RTOF: Receiver timeout
This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE=1 in the USART_CR2 register.
In Smartcard mode, the timeout corresponds to the CWT or BWT timings.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF is set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
kept at reset value.

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ST STM32G471 Specifications

General IconGeneral
BrandST
ModelSTM32G471
CategoryMicrocontrollers
LanguageEnglish

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