Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0440
1668/2126 RM0440 Rev 4
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin.
0: nCTS line set
1: nCTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE=1 in the USART_CR3 register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 LBDF: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software, by
writing 1 to the LBDCF in the USART_ICR.
An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value.
Refer to Section 37.4: USART implementation on page 1595.
Bit 7 TXFNF: TXFIFO not full
TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the
USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO.
This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared
indicating that data can not be written into the USART_TDR.
An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register.
0: Transmit FIFO is full
1: Transmit FIFO is not full
Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending
the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to
writing in TXFIFO (TXFNF and TXFE are set at the same time).
This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit indicates that the last data written in the USART_TDR has been transmitted out of
the shift register.
It is set by hardware when the transmission of a frame containing data is complete and
when TXFE is set.
An interrupt is generated if TCIE=1 in the USART_CR1 register.
TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a
write to the USART_TDR register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
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