FD controller area network (FDCAN) RM0440
1966/2126 RM0440 Rev 4
Transmit cancellation
The FDCAN supports transmit cancellation. To cancel a requested transmission from a Tx
Queue Buffer the Host has to write a 1 to the corresponding bit position (= number of Tx
Buffer) of register TXBCR. Transmit cancellation is not intended for Tx FIFO operation.
Successful cancellation is signaled by setting the corresponding bit of register TXBCF to 1.
In case a transmit cancellation is requested while a transmission from a Tx Buffer is already
ongoing, the corresponding TXBRP bit remains set as long as the transmission is in
progress. If the transmission was successful, the corresponding TXBTO and TXBCF bits
are set. If the transmission was not successful, it is not repeated and only the corresponding
TXBCF bit is set.
Note: In case a pending transmission is canceled immediately before it could have been started,
there is a short time window where no transmission is started even if another message is
pending in the node. This may enable another node to transmit a message that may have a
priority lower than that of the second message in the node.
Tx Event handling
To support Tx event handling the FDCAN has implemented a Tx Event FIFO. After the
FDCAN has transmitted a message on the CAN bus, Message ID and timestamp are stored
in a Tx Event FIFO element. To link a Tx event to a Tx Event FIFO element, the Message
Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element.
The Tx Event FIFO is configured to three elements. The Tx Event FIFO element is
described in Tx FIFO.
The purpose of the Tx Event FIFO is to decouple handling transmit status information from
transmit message handling i.e. a Tx Buffer holds only the message to be transmitted, while
the transmit status is stored separately in the Tx Event FIFO. This has the advantage,
especially when operating a dynamically managed transmit queue, that a Tx Buffer can be
used for a new message immediately after successful transmission. There is no need to
save transmit status information from a Tx Buffer before overwriting that Tx Buffer.
When a Tx Event FIFO full condition is signaled by IR[TEFF], no further elements are
written to the Tx Event FIFO until at least one element has been read out and the Tx Event
FIFO Get Index has been incremented. In case a Tx event occurs while the Tx Event FIFO
is full, this event is discarded and interrupt flag IR[TEFL] is set.
When reading from the Tx Event FIFO, two times the Tx Event FIFO Get Index
TXEFS[EFGI] has to be added to the Tx Event FIFO start address EFSA.
44.3.4 FIFO acknowledge handling
The Get Indices of Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO are controlled by writing to
the corresponding FIFO Acknowledge Index, see Section 44.4.23 and Section 44.4.25.
Writing to the FIFO acknowledge index sets the FIFO Get Index to the FIFO Acknowledge
Index plus one and thereby updates the FIFO Fill Level. There are two use cases:
1. When only a single element has been read from the FIFO (the one being pointed to by
the Get Index), this Get Index value is written to the FIFO Acknowledge Index.
2. When a sequence of elements has been read from the FIFO, it is sufficient to write the
FIFO Acknowledge Index only once at the end of that read sequence (value: Index of
the last element read), to update the FIFO Get Index.
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