Reset and clock control (RCC) RM0440
276/2126 RM0440 Rev 4
LSI or LSE, or in external clock mode.
• The RTC clock which is derived (selected by software) from one of the three following
sources:
– LSE clock
–LSI clock
– HSE clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock which is always the LSI clock.
• The UCPD1 clock, which is derived from HSI16 clock.
• The FDCAN1 clock, which is derived (selected by software) from one of the two
following sources:
– HSE clock
– PLL “Q” clock
– PCLK clock
The RCC feeds the Cortex
®
System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
®
clock (HCLK), configurable in the SysTick Control and Status Register.
FCLK acts as Cortex
®
-M4 with FPU free-running clock. For more details refer to the
Cortex
®
-M4 programming manual (PM0214).
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