Reset and clock control (RCC) RM0440
284/2126 RM0440 Rev 4
7.2.13 Timer clock
The timer clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
7.2.14 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
7.2.15 Clock-out capability
• MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of eight clock signals can be selected as the MCO clock.
–LSI
–LSE
– SYSCLK
–HSI16
–HSI48
–HSE
–PLLCLK
The selection is controlled by the MCOSEL[3:0] bits of the Clock configuration register
(RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the
Clock configuration register (RCC_CFGR).
• LSCO
Another output (LSCO) allows a low speed clock to be output onto the external LSCO
pin:
–LSI
–LSE
This output remains available in Stop (Stop 0 and Stop 1) and Standby modes. The
selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the RTC
domain control register (RCC_BDCR).
The MCO clock output requires the corresponding alternate function selected on the MCO
pin, the LSCO pin should be left in default POR state.
7.2.16 Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17
It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM5, TIM15, TIM16 or TIM17 channel 1 input capture, as represented on Figure 19
Figure 20, Figure 21 and Figure 22.
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