ST STM32G471 User Manual

RM0440 Rev 4 301/2126
RM0440 Reset and clock control (RCC)
338
7.4.9 AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
RNG
RST
Res.
AES
RST
Res. Res. Res. Res.
DAC4
RST
DAC3
RST
DAC2
RST
DAC1
RST
rw rw rw rw rw rw
15141312111098 76543210
Res.
ADC345
RST
ADC12
RST
Res. Res. Res. Res. Res. Res.
GPIOG
RST
GPIOF
RST
GPIOE
RST
GPIOD
RST
GPIOC
RST
GPIOB
RST
GPIOA
RST
rw rw rw rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 RNGRST: RNG reset
Set and cleared by software.
0: No effect
1: Reset RNG
Bit 25 Reserved, must be kept at reset value.
Bit 24 AESRST: AESRST reset
Set and cleared by software.
0: No effect
1: Reset AES
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 DAC4RST: DAC4 reset
Set and cleared by software.
0: No effect
1: Reset DAC4
Bit 18 DAC3RST: DAC3 reset
Set and cleared by software.
0: No effect
1: Reset DAC3
Bit 17 DAC2RST: DAC2 reset
Set and cleared by software.
0: No effect
1: Reset DAC2
Bit 16 DAC1RST: DAC1 reset
Set and cleared by software.
0: No effect
1: Reset DAC1
Bit 15 Reserved, must be kept at reset value.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English