ST STM32G471 User Manual

RM0440 Rev 4 303/2126
RM0440 Reset and clock control (RCC)
338
7.4.10 AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
7.4.11 APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res. QSPIRST Res. Res. Res. Res. Res. Res. Res.
FMC
RST
rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIRST: QUADSPI reset
Set and cleared by software.
0: No effect
1: Reset QUADSPI
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible static memory controller reset
Set and cleared by software.
0: No effect
1: Reset FSMC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
RST
I2C3
RST
Res.
PWR
RST
Res. Res.
FDCAN
RST
Res.
USB
RST
I2C2
RST
I2C1
RST
UART5
RST
UART4
RST
USART3
RST
USART2
RST
Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
RST
SPI2
RST
Res. Res. Res. Res. Res.
CRS
RST
Res. Res.
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw rw rw rw rw rw rw rw rw

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English