ST STM32G471 User Manual

RM0440 Rev 4 333/2126
RM0440 Reset and clock control (RCC)
338
7.4.29 Clock recovery RC register (RCC_CRRCR)
Address: 0x98
Reset value: 0x0000 XXX0
Where X is factory-programmed.
Access: no wait state, word, half-word and byte access
Bits 22:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit
is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if
LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent
Watchdog or by the RTC.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
Set and cleared by software.
0: LSI oscillator OFF
1: LSI oscillator ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
HSI48CAL[8:0] Res. Res. Res. Res. Res.
HSI48
RDY
HSI48
ON
r r rrrr r rr rrw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
They are ready only.
Bits 6:2 Reserved, must be kept at reset value.
Bit 1 HSI48RDY: HSI48 clock ready flag
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is
enabled by software by setting HSI48ON.
0: HSI48 oscillator not ready
1: HSI48 oscillator ready
Bit 0 HSI48ON: HSI48 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
0: HSI48 oscillator OFF
1: HSI48 oscillator ON

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English