Extended interrupts and events controller (EXTI) RM0440
456/2126 RM0440 Rev 4
Note: The reset value for the direct lines is set to ‘1’ in order to enable the interrupt by default.
15.5.8 Event mask register 2 (EXTI_EMR2)
Address offset: 0x24
Reset value: 0x0000 0000
15.5.9 Rising trigger selection register 2 (EXTI_RTSR2)
Address offset: 0x28
Reset value: 0x0000 0000
Bits 31:12 Reserved, must be kept at reset value
Bits 11:8 IMx: Interrupt mask on line x (x = 43 to 40)
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Bits 7:6 Reserved, must be kept at reset value
Bits 5:0 IMx: Interrupt mask on line x (x = 37 to 32)
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. EM43 EM42 EM41 EM40 Res. Res. EM37 EM36 EM35 EM34 EM33 EM32
rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value
Bits 11:8 EMx: Event mask on line x (x = 43 to 40)
0: Event request from line x is masked
1: Event request from line x is not masked
Bits 7:6 Reserved, must be kept at reset value
Bits 5:0 EMx: Event mask on line x (x = 37 to 32)
0: Event request from line x is masked
1: Event request from line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res. RT41 RT40 Res. Res. Res. Res. Res. Res. RT33 RT32
rw rw rw rw
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