Extended interrupts and events controller (EXTI) RM0440
458/2126 RM0440 Rev 4
15.5.10 Falling trigger selection register 2 (EXTI_FTSR2)
Address offset: 0x2C
Reset value: 0x0000 0000
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
15.5.11 Software interrupt event register 2 (EXTI_SWIER2)
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res. FT41 FT40 Res. Res. Res. Res. Res. Res. FT33 FT32
rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:8 FTx: Falling trigger event configuration bit of line x (x = 40 to 41)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 FTx: Falling trigger event configuration bit of line x (x = 32 to 33)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res.
SWI
41
SWI
40
Res. Res. Res. Res. Res. Res.
SWI
33
SWI
32
rw rw rw rw
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