ST STM32G471 User Manual

Analog-to-digital converters (ADC) RM0440
606/2126 RM0440 Rev 4
21.4.3 ADC clocks
Dual clock domain architecture
The dual clock-domain architecture means that the ADC clock is independent from the AHB
bus clock.
The input clock is the same for all ADCs and can be selected between two different clock
sources (see Figure 83: ADC clock scheme):
1. The ADC clock can be a specific clock source, derived from the following clock
sources:
– The system clock
– PLL “P” clock
Refer to RCC Section for more information on how to generate ADC dedicated clock.
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by
a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be
selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different
from “00”.
Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB
prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).
Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in
the ADCx_CCR register.
Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
ADCx_INNi
Negative external analog
input signals
Up to 19 analog input channels (x = ADC number = 1,
2, 3, 4 or 5).
Refer to Section 21.4.4: ADC1/2/3/4/5 connectivity for
details.
ADCx_INPi
Positive external analog
input signals
Up to 19 analog input channels (x = ADC number = 1,
2, 3, 4 or 5).
Refer to Section 21.4.4: ADC1/2/3/4/5 connectivity for
details
Table 160. ADC input/output pins (continued)
Pin name Signal type Comments

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English