RM0440 Rev 4 661/2126
RM0440 Analog-to-digital converters (ADC)
724
Analog watchdog threshold control
LTx[11:0] and HTx[11:0] can be changed when an analog-to-digital conversion is ongoing
(that is between the start of conversion and the end of conversion of the ADC internal state).
If LTx[11:0] and HTx[11:0] are updated during the ADC conversion of the ADC guarded
channel, the watchdog function is masked for this conversion. This masking will be removed
at the next start of conversion, resulting in a analog watchdog thresholds to be applied from
the next ADC conversion. The analog watchdog comparison is performed at each end of
conversion. If the current ADC data is out of the new interval, no interrupt and AWDx_OUT
signal are issued. The Interrupt and the AWD generation only happen at the end of the
conversion which started after the threshold update. If AWD_xOUT is already asserted,
programming the new thresholds does not deassert the AWDx_OUT signal.
Analog watchdog with gain and offset compensation
When gain and offset compensation are enabled, the analog watchdog compares the
threshold after the compensated data.
Note: When the offset compensation is enabled (OFFSETy_EN set to 1 in ADC_OFRy register),
data overflow or underflow can result in a wrong watchdog result. When the saturation is
enabled (SATEN set to 1 in ADC_OFRy), the watchdog provides a correct result. However
this prevents from using the signed data format.
21.4.29 Oversampler
The oversampling unit performs data pre-processing to offload the CPU. It is able to handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:
It allows to perform by hardware the following functions: averaging, data rate reduction,
SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register,
and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to
8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted
right. It is then truncated to the 16 least significant bits, rounded to the nearest value using
the least significant bits left apart by the shifting, before being finally transferred into the
ADC_DR data register.
Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is,
without saturation.
Result
1
M
-----
Conversion t
n
()
n0=
nN1–=
×=
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