RM0440 Rev 4 961/2126
RM0440 High-resolution timer (HRTIM)
1083
Bit 10 SYNCRSTM: Synchronization resets master
This bit enables the master timer reset when receiving a synchronization input event:
0: No effect on the master timer
1: A synchronization input event resets the master timer
Bits 9:8 SYNCIN[1:0] Synchronization input
These bits are defining the synchronization input source.
00: Disabled. HRTIM is not synchronized and runs in standalone mode.
01: Reserved.
10: Internal event on hrtim_in_sync[2]: the HRTIM is synchronized with the on-chip timer (see
Section : Synchronization input).
11: External event on hrtim_in_sync[3]: a positive pulse on HRTIM_SCIN input triggers the HRTIM.
Note: This parameter cannot be changed once the impacted timers are enabled.
Bits 7:6 INTLVD[1:0]: Interleaved mode
This bitfield is significant only when the HALF bit is reset. It enables the interleaved mode.
00: Interleaved mode disabled
01: Triple interleaved mode: when HRTIM_MPER register is written, the HRTIM_MCMP1R active
register is automatically updated with HRTIM_MPER/3 value, and the HRTIM_MCMP2R active
register is automatically updated with 2x (HRTIM_MPER/3) value.
10: Quad interleaved mode: when HRTIM_MPER register is written, the HRTIM_MCMP1R active
register is automatically updated with HRTIM_MPER/4 value, the HRTIM_MCMP2R active
register is automatically updated with HRTIM_MPER/2 value and the HRTIM_MCMP3R active
register is automatically updated with 3x (HRTIM_MPER/4) value.
11: Interleaved mode disabled
Bit 5 HALF: Half mode
This bit enables the half duty-cycle mode: the HRTIM_MCMP1R active register is automatically
updated with HRTIM_MPER/2 value when HRTIM_MPER register is written.
0: Half mode disabled
1: Half mode enabled
Bit 4 RETRIG: Re-triggerable mode
This bit defines the behavior of the master timer counter in single-shot mode.
0: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped (period
elapsed)
1: The timer is re-triggerable: a counter reset is done whatever the counter state (running or stopped)
Bit 3 CONT: Continuous mode
0: The timer operates in single-shot mode and stops when it reaches the MPER value
1: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the
MPER value
Bits 2:0 CKPSC[2:0]: Clock prescaler
These bits define the master timer high-resolution clock prescaler ratio.
The counter clock equivalent frequency (f
COUNTER
) is equal to f
HRCK
/ 2
CKPSC[2:0]
.
The prescaling ratio cannot be modified once the timer is enabled.
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