ST STM32G471 User Manual

High-resolution timer (HRTIM) RM0440
966/2126 RM0440 Rev 4
27.5.5 HRTIM master timer counter register (HRTIM_MCNTR)
Address offset: 0x010
Reset value: 0x0000 0000
27.5.6 HRTIM master timer period register (HRTIM_MPER)
Address offset: 0x014
Reset value: 0x0000 FFDF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
MCNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MCNT[15:0]: Counter value
Holds the master timer counter value. This register can only be written when the master timer is
stopped (MCEN = 0 in HRTIM_MCR).
Note: For HR clock prescaling ratio below 32 (CKPSCCKPSC[2:0] < 5), the least significant bits of the
counter are not significant. They cannot be written and return 0 when read.
Note: The timer behavior is not guaranteed if the counter value is set above the HRTIM_MPER
register value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
MPER[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MPER[15:0]: Master timer period value
This register defines the counter overflow value.
The period value must be above or equal to 3 periods of the f
HRTIM
clock, that is 0x60 if
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
The maximum value is 0x0000 FFDF.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English