ST STM32G471 User Manual

High-resolution timer (HRTIM) RM0440
968/2126 RM0440 Rev 4
27.5.9 HRTIM master timer compare 2 register (HRTIM_MCMP2R)
Address offset: 0x024
Reset value: 0x0000 0000
27.5.10 HRTIM master timer compare 3 register (HRTIM_MCMP3R)
Address offset: 0x028
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
MCMP2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MCMP2[15:0]: Master timer compare 2 value
This register holds the master timer compare 2 value. It is either the preload register or the active
register if preload is disabled.
The compare value must be above or equal to 3 periods of the f
H
RTIM
clock, that is 0x60 if
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
MCMP3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MCMP3[15:0]: Master timer compare 3 value
This register holds the master timer compare 3 value. It is either the preload register or the active
register if preload is disabled.
The compare value must be above or equal to 3 periods of the f
H
RTIM
clock, that is 0x60 if
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English