ST STM32G471 User Manual

RM0440 Rev 4 997/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.28 HRTIM timer x output 2 reset register (HRTIM_RSTx1R) (x = A to F)
Address offset: Block A: 0x0C0
Address offset: Block B: 0x140
Address offset: Block C: 0x1C0
Address offset: Block D: 0x240
Address offset: Block E: 0x2C0
Address offset: Block F: 0x340
Reset value: 0x0000 0000
27.5.29 HRTIM timer x output 2 set register (HRTIM_SETx2R) (x = A to F)
Address offset: Block A: 0x0C4
Address offset: Block B: 0x144
Address offset: Block C: 0x1C4
Address offset: Block D: 0x244
Address offset: Block E: 0x2C4
Address offset: Block F: 0x344
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDAT
E
EXT
EVNT1
0
EXT
EVNT9
EXT
EVNT8
EXT
EVNT7
EXT
EVNT6
EXT
EVNT5
EXT
EVNT4
EXT
EVNT3
EXT
EVNT2
EXT
EVNT1
TIM
EVNT9
TIM
EVNT8
TIM
EVNT7
TIM
EVNT6
TIM
EVNT5
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
TIM
EVNT4
TIM
EVNT3
TIM
EVNT2
TIM
EVNT1
MST
CMP4
MST
CMP3
MST
CMP2
MST
CMP1
MST
PER
CMP4 CMP3 CMP2 CMP1 PER
RESYN
C
SRT
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 Refer to HRTIM_SETx1R bits description.
These bits are defining the source which can force the Tx1 output to its inactive state.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDAT
E
EXT
EVNT1
0
EXT
EVNT9
EXT
EVNT8
EXT
EVNT7
EXT
EVNT6
EXT
EVNT5
EXT
EVNT4
EXT
EVNT3
EXT
EVNT2
EXT
EVNT1
TIM
EVNT9
TIM
EVNT8
TIM
EVNT7
TIM
EVNT6
TIM
EVNT5
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
TIM
EVNT4
TIM
EVNT3
TIM
EVNT2
TIM
EVNT1
MST
CMP4
MST
CMP3
MST
CMP2
MST
CMP1
MST
PER
CMP4 CMP3 CMP2 CMP1 PER
RESYN
C
SST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 Refer to HRTIM_SETx1R bits description.
These bits are defining the source which forces the Tx2 output to its active state.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English