RM0440 Rev 4 999/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.31 HRTIM timer x external event filtering register 1 (HRTIM_EEFxR1)
(x = A to F)
Address offset: Block A: 0x0CC
Address offset: Block B: 0x14C
Address offset: Block C: 0x1CC
Address offset: Block D: 0x24C
Address offset: Block E: 0x2CC
Address offset: Block F: 0x34C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. EE5FLTR[3:0]
EE5LT
CH
Res. EE4FLTR[3:0]
EE4LT
CH
Res.
EE3FL
TR[3]
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
EE3FLTR[2:0]
EE3LT
CH
Res. EE2FLTR[3:0]
EE2LT
CH
Res. EE1FLTR[3:0]
EE1LT
CH
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:25 EE5FLTR[3:0]: External event 5 filter
Refer to EE1FLTR[3:0] description.
Bit 24 EE5LTCH: External event 5 latch
Refer to EE1LTCH description
Bit 23 Reserved, must be kept at reset value.
Bits 22:19 EE4FLTR[3:0]: External event 4 filter
Refer to EE1FLTR[3:0] description.
Bit 18 EE4LTCH: External event 4 latch
Refer to EE1LTCH description
Bit 17 Reserved, must be kept at reset value.
Bits 16:13 EE3FLTR[3:0]: External event 3 filter
Refer to EE1FLTR[3:0] description.
Bit 12 EE3LTCH: External event 3 latch
Refer to EE1LTCH description
Bit 11 Reserved, must be kept at reset value.
Bits 10:7 EE2FLTR[3:0]: External event 2 filter
Refer to EE1FLTR[3:0] description.
Bit 6 EE2LTCH: External event 2 latch
Refer to EE1LTCH description.