ST STM32L4 5 Series User Manual

DocID024597 Rev 5 31/1830
RM0351 Contents
48
32.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1113
32.6.1 TIM16/TIM17 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 1113
32.6.2 TIM16/TIM17 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . 1114
32.6.3 TIM16/TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 1115
32.6.4 TIM16/TIM17 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 1116
32.6.5 TIM16/TIM17 event generation register (TIMx_EGR) . . . . . . . . . . . . 1117
32.6.6 TIM16/TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . 1118
32.6.7 TIM16/TIM17 capture/compare enable register (TIMx_CCER) . . . . . 1120
32.6.8 TIM16/TIM17 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
32.6.9 TIM16/TIM17 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 1123
32.6.10 TIM16/TIM17 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 1123
32.6.11 TIM16/TIM17 repetition counter register (TIMx_RCR) . . . . . . . . . . . 1124
32.6.12 TIM16/TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 1124
32.6.13 TIM16/TIM17 break and dead-time register (TIMx_BDTR) . . . . . . . . 1125
32.6.14 TIM16/TIM17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 1127
32.6.15 TIM16/TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . . . . 1127
32.6.16 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1128
32.6.17 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1128
32.6.18 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1129
32.6.19 TIM17 option register 2 (TIM17_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1130
32.6.20 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
33 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
33.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1134
33.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1134
33.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1135
33.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
33.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
33.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
33.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
33.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
33.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1141
33.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 1141
33.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 1143
33.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 1143
33.4.4 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1144
33.4.5 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 1144

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English