ST STM32L4 5 Series User Manual

DocID024597 Rev 5 9/1830
RM0351 Contents
48
8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I) . . . . . . . . . . 302
8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A..I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A..I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
8.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A..I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
8.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..I) . . . . . . . . . . . . . . 305
8.4.12 GPIO port analog switch control register (GPIOx_ASCR)(x = A..H) . . 305
8.4.13 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 309
9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 309
9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 310
9.2.3 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
9.2.4 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.2.5 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
9.2.6 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 318
9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 319
9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 320
9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 320
9.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . 321
9.2.12 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
10 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
10.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
10.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to
timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) . . . . . . . . . . . . . . . . 326
10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC
(ADC1/ADC2/ADC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English