Signal Descriptions 5-31
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.6 AP (Address Parity)
Bidirectional
Summary AP carries the even parity bit for cache line addresses driven
and sampled on A31–A5. The processor drives AP when it
drives an address for a read or write cycle. The processor sam-
ples AP during inquire cycles in order to drive the APCHK out-
put.
Driven, Sampled, and
Floated
AP is driven, sampled, and floated with the same timing as
A31–A3. See the description of A31–A3 on page 5-20.
Details The bit value driven on AP is counted with the bit values
driven on A31–A5 to determine address parity. If the total
number of 1 bits is even on AP and A31–A5, the address is con-
sidered free of error (thus the term even parity). If the total
number of 1 bits is odd, the address is considered to have an
error. The bit values driven on A4–A3 are not counted during
the parity checking.
In addition to generating and checking address parity, the pro-
cessor also generates and checks data parity using the DP7–
DP0 and PCHK signals. See page 5-57 and 5-101 for details.
Unlike the handling of PCHK, however, the processor does not
capture the faulty address in a register when it asserts
APCHK. System logic must handle the error externally. Typi-
cal PC systems assert an interrupt signal such as NMI after a
parity error is detected.
Systems that do not implement address parity generation and
checking should tie AP either High or Low and ignore the
APCHK output.
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