AMD K5

Cache and TLB Testing 7-13
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 7-6. Test Formats: Instruction-Cache Instructions
EDX: Array Pointer
031 30 29 28 27
0 0
Array ID
(E4h)
Way
0 0 0 0 0 0 0 0
Set
0
EAX: Test Data
(E4h) Instruction Bytes
720 19
981112
Opcode
Bytes
0
0 0 0 0 0 0
Valid Bits
31 26 25