AMD K5 User Manual

6-30 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.3.5 Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area specifies if SMM was entered from
the Halt state. Before returning from SMM, the halt restart slot
can be written by the SMM service routine to specify whether
the return from SMM should take the processor back to the
Halt state or to the instruction-execution state specified by the
SMM state-save area.
On entry into SMM, the halt restart slot is configured as fol-
lows:
■ Bits 15–1—Undefined
■ Bit 0—Point of entry to SMM:
1 = entered from Halt state.
0 = not entered from Halt state
Before return from SMM, the halt restart slot can be written
as:
■ Bits 15–1—Undefined
■ Bit 0—Point of return from SMM
1 = return to Halt state
0 = return to state specified by SMM state-save area
The fields of the halt restart slot are the same as in the Pen-
tium processor auto halt restart slot. During entry into and exit
from SMM, the processor writes or reads only bit 0 of the 16-bit
value although the entire 16 bits can be read or written by the
service routine. The Pentium-compatible pseudo-code for
implementing the halt restart slot in BIOS is as follows:
begin
{
if return to Halt state then
{
if SMI# during Halt state then
set halt restart slot to 00FFh
}
}end
If the return takes the processor back to the Halt state, the
HLT instruction is not refetched, but the Halt special bus cycle
is driven on the bus after the return.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm