AMD K5 User Manual

4-8 Performance
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
4.2.2 Integer Instructions
Table 4-1 shows the execution-unit usage for each integer
instruction, along with relative cycle numbers for dispatch and
execution of the associated ROPs for the instruction.
Table 4-1. Integer Instructions
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing
ADD reg, reg 0_0x_000000xx_xxx_xxx Falu1/1
ADD reg, mem 0_1x_0000001x_xxx_xxx F
ld 1/1
alu 1/2
ADD mem, reg 0_1x_0000000x_xxx_xxx F
ld 1/1
alu 1/2
st 1/1/3
ADD AL/AX/EAX, imm 0_xx_0000010x_xxx_xxx Falu1/1
ADD reg, imm 0_0x_100000xx_000_xxx Falu1/1
ADD mem, imm 0_1x_100000xx_000_xxx F
ld 1/1
alu 1/2
st 1/1/3
AND reg, reg 0_0x_001000xx_xxx_xxx Falu1/1
AND reg, mem 0_1x_0010001x_xxx_xxx F
ld 1/1
alu 1/2
AND mem, reg 0_1x_0010000x_xxx_xxx F
ld 1/1
alu 1/2
st 1/1/3
AND AL/AX/EAX, imm 0_xx_0010010x_xxx_xxx Falu1/1
AND reg, imm 0_0x_100000xx_100_xxx Falu1/1
AND mem, imm 0_1x_100000xx_100_xxx F
ld 1/1
alu 1/2
st 1/1/3
BSF reg, reg 1_0x_10111100_xxx_xxx Falu11/1
BSF reg, mem 1_1x_10111100_xxx_xxx F
ld 1/1
alu1 1/2
BSR reg, reg 1_0x_10111101_xxx_xxx Falu11/1
BSR reg, mem 1_1x_10111101_xxx_xxx F
ld 1/1
alu1 1/2
BSWAP reg 1_xx_11001xxx_xxx_xxx Falu11/1
BT reg, reg 1_0x_10100011_xxx_xxx Falu11/1

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm