Signal Descriptions 5-45
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.13 BREQ (Bus Request)
Output
Summary The processor asserts BREQ to indicate that it is either driving
a cycle on the bus, performing certain types of cache accesses,
or needs access to the bus in order to continue operating.
Driven The processor asserts BREQ on the first clock of every proces-
sor-initiated bus cycle, with ADS, and in the first clock of every
cache store and cache-tag recovery. The processor asserts
BREQ continuously while it being held off the bus and can no
longer operate out of its cache.
BREQ is driven during memory cycles (including cache
writethroughs and writebacks), I/O cycles, locked cycles, spe-
cial bus cycles, and interrupt acknowledge operations in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM; or while AHOLD, BOFF, HLDA, or PRDY is
asserted. BREQ is not driven in the Shutdown, Halt, Stop
Grant, or Stop Clock states; or while RESET or INIT is
asserted.
Details The processor observes a bus-parking protocol. It continues to
drive the bus without an arbitration sequence in the absence of
AHOLD, BOFF or HOLD. System logic can use the assertion of
BREQ to arbitrate bus access among competing bus masters. If
the processor asserts BREQ only on the first clock of a cache
access or bus cycle, system logic need not take action, whether
or not the processor is being held off the bus. If the processor
can no longer operate out of cache, it holds BREQ asserted
until system logic negates the signal that is holding it off the
bus (AHOLD, BOFF, or HOLD). One clock after the negation of
that signal, the processor drives a bus cycle with ADS.
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