AMD K5 User Manual

5-64 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.22 FERR (Floating-Point Error)
Output
Summary The processor asserts FERR to report the occurrence of an
unmasked floating-point exception resulting from the execu-
tion of a floating-point instruction. This signal is provided to
allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR signal.
Driven The processor drives FERR every clock during memory cycles
(including cache writethroughs and writebacks), cache hits of
all types, I/O cycles, and locked cycles in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM. FERR
is not driven during the Shutdown, Halt, Stop Grant, or Stop
Clock states, or while RESET, INIT, or PRDY is asserted.
Details The processor asserts FERR on the instruction boundary of the
next floating-point instruction or WAIT instruction that occurs
following the floating-point instruction that caused the
unmasked floating-point exception—that is, FERR is not
asserted at the time the exception occurs. The IGNNE signal
does not affect the assertion of FERR.
FERR is negated during the following conditions:
■ Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
■ Under certain circumstances, following the successful exe-
cution of the floating-point instructions FLDCW, FLDENV,
and FRSTOR, which load the floating-point status word or
the floating-point control word
■ Following the rising transition of RESET
FERR is always driven except in Tri-State Test mode.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm