5-132 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.55 W/R (Write or Read)
Output
Summary The processor drives W/R to indicate whether it is performing
a write or read cycle on the bus. The signal is driven at the
same time as the other two cycle definition signals: D/C and
M/IO. A specific encoding of D/C, M/IO and W/R identifies one
of several special bus cycles.
Driven and Floated W/R is driven and floated with the same timing as D/C. See the
description of D/C on page 5-53.
Details The processor drives W/R according to whether the access is
initiated by the processor’s fetch logic (which can initiate only
reads) or its load/store logic (which can initiate reads or writes
of operands). Such accesses can be done speculatively. Before
the processor fetches an instruction or reads or writes a data
operand, it checks the associated code or data segment
descriptor to verify that such action is permitted. The execute
(E) bit in the segment descriptor maintained by the operating
system distinguishes between data and code segments, and the
(R/W) bit specifies the segment’s read and write properties.
Code segments can only be read; data and stack segments can
read-only or read-write.
The processor specifies all special bus cycles with D/C = 0,
M/IO = 0 and W/R = 1. The cycles are then differentiated by
BE7–BE0 and A31–A3.
At the falling edge of RESET, the states of BRDYC and BUS-
CHK control the drive strength on the A21–A3 (not including
A31–A22), ADS, HITM, and W/R signals. The drive strength is
weak for all states of BRDYC and BUSCHK except when
BRDYC and BUSCHK are both Low, in which case the drive
strength is strong. The A31–A22 signals use the weak drive
strength at all times. See the data sheet for details.
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