AMD K5 User Manual

5-68 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.24 FRCMC (Functional-Redundancy Check Master/Checker)
Input
Summary If FRCMC is asserted at RESET, the processor enters Func-
tional-Redundancy Checking mode, as the checker, and
reports checking errors on the IERR output. If FRCMC is
negated at RESET, the processor operates normally, although
it also behaves as the master in a functional-redundancy check-
ing arrangement with a checker.
Sampled The processor samples FRCMC at the falling edge of RESET.
The processor does not sample FRCMC at any other time.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
Details In the Functional-Redundancy Checking mode, two processors
have their signals tied together. One processor (the master)
operates normally. The other processor (the checker) has its
output and bidirectional signals (except for TDO and IERR)
floated to detect the state of the master’s signals. The master
controls instruction fetching and the checker mimics its behav-
ior by sampling the fetched instructions as they appear on the
bus. Both processors execute the instructions in lock step. The
checker compares the state of the master’s output and bidirec-
tional signals with the state that the checker itself would have
driven for the same instruction stream. Errors detected by the
checker are reported on the checker’s IERR output. On the
AMD-K5 processor, the IERR output is reserved solely for
functional-redundancy checking; no other errors are reported
on that output.
Functional-redundancy checking is typically implemented on
single-processor, fault-monitoring systems (which actually
have two processors). The master processor runs the opera-
tional programs and the checker processor is dedicated
entirely to constant checking. In this arrangement, the test of
accurate operation consists solely of reporting one or more
errors; the particular type of error or the instruction causing
an error is not reported. The arrangement works because the
processor is entirely deterministic. Speculative prefetching,
speculative execution, and cache replacement all occur in
identical ways and at identical times on both processors, if

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm