AMD K5

3-32 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
3.3.4 RDTSC
mnemonic opcode description
RDTSC 0F31 Read time stamp counter
Privilege: Selectable by TSD bit in CR4
Registers Affected: EAX, EDX
Flags Affected: none
Exceptions Generated: Real, Virtual-8086 mode—Invalid Opcode
Protected mode—GP (0) if CPL not = 0 when CR4.TSD = 1
The processor’s 64-bit time stamp counter (TSC) increments on each processor clock.
In Real or Protected mode, the counter can be read with the RDMSR instruction and
written with the WRMSR instruction when CPL = 0. However, in Protected mode the
RDTSC instruction can be used to read the counter at privilege levels higher than
CPL = 0.
The required privilege level for using the RDTSC instruction is determined by the
Time Stamp Disable (TSD) bit in CR4, as follows:
■ CPL = 0—Set the TSD bit in CR4 to 1
■ Any CPL—Clear the TSD bit in CR4 to 0
The RDTSC instruction reads the counter value into the EDX and EAX registers as
follows:
■ EDX—Upper 32 bits of TSC
■ EAX—Lower 32 bits of TSC
The following example shows how the RDTSC instruction can be used. After this
code is executed, EAX and EDX contain the time required to execute the RDTSC
instruction.
mov ecx,10h ;Time Stamp Counter Access via MSRs
mov eax,00000000h ;Initialize the Counter to zero
db 0Fh, 30h ;WRMSR
db 0Fh, 31h ;RDTSC
db 0Fh, 31h ;RDTSC