AMD K5

Control Register 4 (CR4) Extensions 3-15
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 3-6. EFLAGS Register
Table 3-4. Virtual-Interrupt Additions to EFLAGS Register
Bit Mnemonic Description Function
20 VIP
Virtual Interrupt Pend-
ing
Set by the operating system (via the EFLAGS image on the stack)
when an external maskable interrupt (INTR) occurs for a Virtual-
8086 program who’s VIF bit is cleared. The bit is checked by the
processor when the program subsequently attempts to set VIF.
19 VIF Virtual Interrupt Flag
When the VME bit in CR4 is set, the VIF bit is modified by the
processor when a Virtual-8086 program running at less privilege
than the IOPL attempts to modify the IF bit. The VIF bit is used by
the operating system to determine whether a maskable interrupt
should be passed on to the program or held pending.
ID Flag ID 21
Virtual Interrupt Pending VIP 20
Virtual Interrupt Flag VIF 19
Alignment Check AC 18
Virtual-8086 Mode VM 17
Resume Flag RF 16
Nested Task NT 14
I/O Privilege Level IOPL 13–12
Overflow Flag OF 11
Direction Flag DF 10
Interrupt Flag IF 9
Trap Flag TF 8
Sign Flag SF 7
Zero Flag ZF 6
Auxiliary Flag AF 4
Parity Flag PF 2
Carry Flag CF 0
9876543210101112131415161718192021
I
O
P
L
31 30 29 28 27 26 25 24 23 22
A
F
P
F
Z
F
S
F
I
F
D
F
T
F
O
F
N
T
R
F
V
M
A
C
V
I
F
V
I
P
I
D
C
F
Reserved