AMD K5 User Manual

Cache 6-19
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
HOLD Arbitration System logic can use the HOLD (request) and HLDA (acknowl-
edge) protocol to gain control of the address and data buses.
Like BOFF, HOLD/HLDA gains control of both the address and
data buses but only after the processor completes any in-
progress bus cycle or a sequence of cycles, like a locked cycle.
However, unlike BOFF, the HOLD/HLDA protocol cannot
resolve deadlock. In systems where deadlock can occur BOFF
must be used, and there is no need to support HOLD/HLDA.
6.2.6 Write-Once Protocol
Among the several write protocols that can be implemented by
the L1 and L2 caches, the write-once protocol is of special
interest for systems in which the processor has an L2 cache on
a separate bus from other caching masters. In such designs, the
write-once protocol allows caching masters to simultaneously
cache shared copies of data until one of the masters writes to
that location, at which time the writing master can have the
data exclusively and other caching masters must invalidate
their copies. The protocol allows other masters to determine
whether the processor has a modified line in its L1 cache by
driving an inquire cycle to the L2 cache, and it allows other
masters, via inquire cycles, to intervene in the processor’s
exclusive use of the data.
Figure 6-5 shows an example. System logic drives separate WB/
WT input signals to the L1 and L2 cache. During line fills and
writes to the L1 cache, the protocol then works as follows:
1. During a read miss, the processor fills a line in the L1. At
the same time, system logic (or the L2) fills a line in the L2
with the same data, and drives the WB/WT input Low
(writethrough) to both the L1 and L2. This leaves the L1
and L2 caches as follows:
L1 cache line in the shared state
L2 cache line in the shared state
2. During the first write to that line, the processor updates the
shared line in the L1 and L2, and writes through to memory.
At the same time, system logic drives the L1 WB/WT input
Low (writethrough) and the L2 WB/WT input High (write-
back). This leaves the L1 and L2 caches as follows:
L1 cache line in the shared state
L2 cache line in the exclusive state

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm