AMD K5 User Manual

5-58 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.20 EADS (External Address Strobe)
Input
Summary While system logic holds the processor off the address bus, sys-
tem logic can assert EADS and drive a cache line address to
initiate an inquire cycle. Inquire cycles cause the processor to
snoop its internal caches.
Sampled The processor samples EADS every clock, beginning two clocks
after the assertion of AHOLD or BOFF, or one clock after the
assertion of HLDA; except while the processor drives A31–A3,
while it asserts HITM, and one clock after EADS.
While AHOLD is asserted, EADS is sampled while the proces-
sor finishes an in-progress memory cycle (including a cache
writethrough or writeback), I/O cycle, locked cycle, special bus
cycle, or interrupt acknowledge operation in the normal oper-
ating modes (Real, Protected, and Virtual-8086) and in SMM.
While AHOLD, BOFF, or HLDA is asserted, EADS is always
sampled while the processor operates out of its cache or is idle;
or is in the Shutdown, Halt, or Stop Grant state; or while INIT
or PRDY is asserted. EADS is not sampled in the Stop Clock
state or while RESET is asserted.
If BOFF and EADS are both asserted in the same clock that
AHOLD is negated, EADS is not recognized. If EADS is
asserted on the same clock that HOLD is negated, both the
AMD-K5 and the Pentium processors recognize this as a valid
inquire cycle and process it correctly. However, if EADS is
asserted on the clock following the negation of HOLD, the
AMD-K5 processor does not recognize this as a valid inquire
cycle.
Details Inquire cycles cause the processor to compare a physical
address driven by system logic with the processor’s physical
address tags for its instruction and data caches. Inquire cycles
can occur in parallel with the processor’s own cache accesses,
which are done through a separate set of linear address tags.
Inquire cycles are sometimes called snoop cycles, although the
term snoop means at least three different things: (a) external
snoop cycles that are occasionally driven on the bus by system
logic, such as an inquire cycle, (b) internal snoops that are
done automatically whenever the processor accesses its cache,
such as when the processor compares the address of a write to

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm