AMD K5

Signal Descriptions 5-59
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
its data cache with the addresses in the instruction cache, and
(c) automatic bus watching, in which a caching device con-
stantly compares addresses being driven by any other device
on the address bus with its own cached addresses. The AMD-K5
and Pentium processors only support the first two types of
snooping, not the third.
There are three methods by which system logic can obtain con-
trol of the address bus prior to running one or more inquire
cycles: AHOLD, BOFF or HOLD. While it has control of at least
the address bus, system logic can drive inquire cycles using
EADS, A31–A5, INV, and (optionally) AP.
The system logic’s sequence for driving inquire cycles is as fol-
lows:
1. Assert AHOLD, BOFF, or HOLD to obtain at least the
address bus.
2. Assert EADS two clocks after asserting AHOLD or BOFF, or
one clock after the processor asserts HLDA, and simulta-
neously drive INV and a cache-line address on A31–A5. The
processor latches the address on A31–A5 when EADS is
asserted.
3. Wait two clocks, watching for HITM and/or HIT to be
asserted:
• If neither HIT nor HITM are asserted at the end of two
clocks, or if only HIT is asserted, the inquire cycle termi-
nates. EADS can be asserted again in the same clock
that HITM is negated.
• If HITM is asserted, a writeback follows and the proces-
sor does not recognize EADS again until one clock after
the last BRDY of the writeback. The timing of the write-
back depends on whether AHOLD, BOFF or HOLD was
asserted to gain access to the bus: if AHOLD was used,
the processor begins driving the four-transfer burst
writeback as early as two clocks after asserting HITM,
whether or not AHOLD is still asserted. If BOFF or
HOLD was used, the processor delays the writeback un-
til after BOFF or HLDA is negated.
To prevent multiple inquire cycles from hitting modified lines,
and causing a backlog of writebacks, the processor does not
recognize another EADS while HITM is asserted. HITM is