AMD K5

5-60 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
negated one clock after the last BRDY of the writeback, at
which time another EADS can be asserted.
If AHOLD is held asserted throughout an inquire cycle, system
logic must latch the inquire cycle address when EADS is
asserted. This is required so that, if the inquire cycle hits a
modified line, the address used for the writeback need not be
driven by the processor when the processor asserts ADS for the
writeback; instead, system logic must use its latched copy of
the inquire cycle address. By contrast, if system logic always
negates AHOLD before the writeback, the processor will drive
the writeback address when it asserts ADS for the writeback,
and system logic need not latch a copy of the inquire cycle
address.
If EADS is asserted in the same clock that HOLD is negated,
the processor recognizes this as a valid inquire cycle. However,
if EADS is asserted in the clock following the negation of
HOLD, the processor does not recognize this as a valid inquire
cycle.
Inquire cycles can be implemented for every memory access by
another caching master. To do this, system logic can generate
EADS to the processor using the equivalent of ADS from the
other caching master.
An inquire cycle can hit a line that is in the process of being
written back for a reason other than the inquire, such as when
the writeback is being done to make room in the cache for a
new line (called a replacement writeback) or when the
WBINVD (writeback and invalidate) instruction is being exe-
cuted. If this occurs, the in-progress writeback completes but
the system must recognize that this writeback was for the same
line that was the subject of the inquire cycle. The processor
will not repeat the writeback, but it will assert HITM.
If an inquire cycle occurs during a Branch-Trace Message spe-
cial cycle, the branch-address information driven by the pro-
cessor on A31–A3 can be overwritten by the inquiring bus
master. In such cases, system logic should latch A31–A3 when
ADS is asserted (that is, before asserting AHOLD, BOFF or
HOLD).
EADS should not be asserted at the same time the processor is
running a BIST (INIT asserted on the falling edge of RESET) or