AMD K5

Bus Cycle Timing 5-189
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.4.7 Mode Transitions, Reset, and Testing
System logic can control the system-management, clocking,
and initialization states of the processor with SMI, STPCLK,
INIT, and RESET. The following examples shows the proces-
sor’s response to some of the signals.
Transition from
Normal Execution to
SMM
Figure 5-26A and Figure 5-26B shows the transition from one of
the processor’s normal operating modes (Real, Protected, or
Virtual-8086 mode) to System Management Mode (SMM). Sys-
tem logic causes this transition by asserting SMI.
Upon recognizing an SMI interrupt at the next instruction-
retirement boundary, the processor performs the following
actions:
1. Flush Pipeline—The processor invalidates all instructions
remaining in the pipeline. This is not visible on the bus.
2. Complete In-Progress Cycle—If the processor had begun a
bus cycle when SMI was asserted, the processor completes
the bus cycle and waits until the system asserts the last
expected BRDY and also asserts EWBE. In Figure 5-26A, a
burst read is shown completing after SMI is asserted.
3. Acknowledge—After sampling EWBE asserted, the proces-
sor asserts SMIACT to acknowledge the interrupt. This is
visible on the bus after SMI is recognized. At that point, sys-
tem logic must ensure that all memory accesses during
SMM are to the SMM memory space.
4. Save Processor State—The processor saves its state in the
SMM state-save area. These saves appear at the far right of
the example in Figure 5-26B.
5. Disable Interrupts and Debug Traps—The processor disables
maskable interrupts by clearing the interrupt flag (IF) in
EFLAGS, disables NMI interrupts, clears the trap flag (TF)
in EFLAGS, and clears the DR7–DR6 debug control and sta-
tus registers. This is not visible on the bus.
6. Service Interrupt—The processor jumps to the entry point of
the SMM service routine at the SMM base physical address,
whose default is 0003_8000h in SMM memory.
For details on SMM, see Section 6.3 on page 6-23.