Memory 6-1
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
6
System Design
This chapter summarizes topics that may be of help to system
board designers. The discussions touch on the design of mem-
ory, cache, System Management Mode (SMM), clock control
(power management), and a few other topics. Many of the
details that relate to this subject are also covered in Chapter 5,
which describes the processor’s signals and bus cycles not only
from the processor’s view, but also from the system’s view.
Throughout this chapter, the term clock refers both to the pro-
cessor’s internal clock and to the bus clock (CLK). Thus, each
type of clock is explicitly differentiated in the descriptions
that follow.
6.1 Memory
The processor can be configured for memory bus speeds of 50,
60, or 66 MHz. Main memory can be built from Page-mode or
EDO (extended data out) DRAM. On a 66-MHz bus, the read-
cycle time for a page hit in EDO DRAM is 7-2-2-2 (7 clocks for
the first transfer and 2 clocks for each remaining transfer) and
10-2-2-2 for a page miss. The read-cycle time for a page-hit
Page-mode DRAM at 66 MHz is 7-4-4-4 and 10-4-4-4 for a page
miss. On a 50-MHz bus, there is no change in timing for EDO
DRAM but Page-mode DRAM timing becomes 6-3-3-3 for a
page hit and 8-3-3-3 for a page miss.
To Next Page
Loading...
Need help?
General
