AMD K5 User Manual

Cache and TLB Testing 7-11
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 7-4. Test Formats: Data-Cache Data
EDX: Array Pointer
031 30 29 28 27
0 0
Array ID
(E0h)
Way
0 0 0 0 0 0 0 0 0
Set
0 0
EAX: Test Data
(E0h) Data
0
Valid Bits
71819
31
98101213
Dword

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm