AMD K5 User Manual

5-44 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.12 BRDYC (Burst Ready)
Input
Summary BRDYC is an identical copy of BRDY, except that BRDYC has
an internal pullup resistor whereas BRDY does not. In systems
that would otherwise place large capacitive loads on BRDY,
the BRDYC output can be used in place of BRDY to distribute
loads, thereby increasing response times.
Sampled BRDYC is sampled with the same timing as BRDY. See the
description of BRDY on page 5-41.
Details See the description of BRDY on page 5-41. Unlike BRDY,
BRDYC has an internal pullup resistor.
At the falling edge of RESET, the states of BRDYC and BUS-
CHK control the drive strength on the A21–A3 (not including
A31–A22), ADS, HITM, and W/R signals. The drive strength is
weak for all states of BRDYC and BUSCHK except when
BRDYC and BUSCHK are both Low, in which case the drive
strength is strong. The A31–A22 signals use the weak drive
strength at all times. See the data sheet for details.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm