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18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
7
Test and Debug
The AMD-K5 processor has the following modes in which pro-
cessor and system operation can be tested or debugged:
■ Hardware Configuration Register (HWCR)—The HWCR is a
model-specific register that contains configuration bits that
enable cache, branch tracing, debug, and clock control func-
tions.
■ Built-In Self-Test (BIST)—Both normal and test access port
(TAP) BIST.
■ Output-Float Test—A test mode that causes the AMD-K5
processor to float all of its output and bidirectional signals.
■ Cache and TLB Testing—The Array Access Register (AAR)
supports writes and reads to any location in the tag and
data arrays of the processor’s on-chip caches and TLBs.
■ Debug Registers—Standard 486 debug functions, with an I/O-
breakpoint extension.
■ Branch Tracing—A pair of special bus cycles can be driven
immediately after taken branches to specify information
about the branch instruction and its target. The Hardware
Configuration Register (HWCR) provides support for this
and other debug functions.
■ Functional Redundancy Checking—Support for real-time
testing using two processors in a master-checker relation-
ship.
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