AMD K5 User Manual

A-6
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
On an unlocked and non-cacheable CMPXCHG8B operation,
the misaligned and aligned CMPXCHG8B operations are the
same as the locked misaligned and locked aligned
CMPXCHG8B operations, respectively, described above.
On an unlocked and cacheable CMPXCHG8B operation, the
AMD-K5 and Pentium processors behave the same.
A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles
The AMD-K5 processor performs split (misaligned) memory
read, memory write, and I/O read cycles in the reverse order of
the Pentium processor. Split I/O write cycles occur in the same
order on both processors.
A.2.4 Halt Cycle after FLUSH
When halted, the AMD-K5 processor reruns a Halt special
cycle after the Flush Acknowledge special cycle following a
cache flush operation. The Pentium processor does not rerun a
Halt special cycle.
A.2.5 Selectable Drive Strengths on Output Driver
The AMD-K5 processor supports selectable drive strengths on
the following output pins:
■ A20–A3
■ W/R
■ ADS
■ HITM
This is the same set of output pins that have selectable drive
strengths on the Pentium processor. However, the Pentium
processor supports three drive strengths on these pins while
the AMD-K5 processor supports two.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm