AMD K5 User Manual

6-2 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.1.1 Memory Map
Figure 6-1 shows a typical physical memory map for a DOS-
based desktop system after DOS boots. Various regions of this
memory map to RAM or ROM on the motherboard and adapter
boards. The processor hardware imposes only two constraints
on the physical memory map implemented by system hard-
ware—the boot address at FFFF_FFF0h, which is accessed
when RESET or INIT is asserted, and the default addresses for
SMM. However, other physical memory mapping requirements
are imposed by BIOS, the operating system, and the specific
hardware implemented for the system. In general, the conven-
tions for hardware memory mapping for DOS-based desktop
systems include the following:
■ Memory-decoder aliasing of boot ROM space
■ Cacheable vs. noncacheable address spaces
■ SMM memory address space (optional)
Each of these issues is summarized briefly in the sections that
follow.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm