AMD K5

3-8 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Table 3-2. Page-Directory Entry (PDE) Fields
Bit Mnemonic Description Function
31–12 BASE
Physical Base
Address
For 4-Kbyte pages, bits 31–12 contain the physical base address of
a 4-Kbyte page table.
For 4-Mbyte pages, bits 31–22 contain the physical base address
of a 4-Mbyte page and bits 21–12 must be cleared to 0. (The pro-
cessor will generate a page fault if bits 21–12 are not cleared to 0.)
11–9 AVL Available to Software
Software may use this field to store any type of information. When
the page-directory entry is not present (P bit cleared), bits 31–1
become available to software.
8 G Global 0 = local, 1 = global.
7 PS Page Size 0 = 4-Kbyte, 1 = 4-Mbyte.
6 D Dirty
For 4-Kbyte pages, this bit is undefined and ignored. The proces-
sor does not change it.
0 = not written, 1 = written.
For 4-Mbyte pages, the processor sets this bit to 1 during a write
to the page that is mapped by this page-directory entry.
0 = not written, 1 = written.
5 A Accessed
The processor sets this bit to 1 during a read or write to any page
that is mapped by this page-directory entry.
0 = not read or written, 1 = read or written.
4 PCD Page Cache Disable
Specifies cacheability for all pages mapped by this page-directory
entry. Whether a location in a mapped page is actually cached
also depends on several other factors.
0 = cacheable page, 1 = non-cacheable.
3 PWT Page Writethrough
Specifies writeback or writethrough cache protocol for all pages
mapped by this page-directory entry. Whether a location in a
mapped page is actually cached in a writeback or writethrough
state also depends on several other factors.
0 = writeback page, 1 = writethough page.
2 U/S User/Supervisor 0 = user (any CPL), 1 = supervisor (CPL < 3).
1 W/R Write/Read 0 = read or execute, 1 = write, read, or execute.
0 P Present 0 = not valid, 1 = valid.