AMD K5

Bus Cycle Timing 5-183
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
FLUSH-Acknowledge
Cycle
Figure 5-22 shows the FLUSH-acknowledge special bus cycle,
which the processor drives in response to system logic’s asser-
tion of FLUSH. This example shows the processor completing
other unrelated bus cycles following the assertion of FLUSH.
These bus cycles are caused by the execution of instructions
earlier in the pipeline, which are completing execution before
the processor recognizes FLUSH on the next instruction-retire-
ment boundary.
FLUSH causes the processor to write back all modified lines in
its data cache. Only one such writeback is shown in this exam-
ple. After all writebacks complete, the processor invalidates
all lines in both of its caches. Then, the processor generates the
FLUSH-acknowledge special bus cycle (BE7–BE0 = EFh) to
indicate that the writebacks and invalidation have completed.
System logic must respond by asserting BRDY.
Figure 5-22. FLUSH-Acknowledge Cycle
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
FLUSH
KEN
LOCK
M/IO
W/R
CLK
Flush Asserted
Writeback
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