AMD K5

Cache 6-21
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 6-5. Write-Once Protocol
WB/WT = 0
WB/WT = 1
WB/WT = 0
WB/WT = 0
Line Fill
System Bus
Other
Bus
Master
System
Logic
AMD-K5
Processor
Main
Memory
Look-Through
L2 Cache
1
WB/WT = 1
2
3
1
2
Writethrough
Writethrough
1
2
3