AMD K5 User Manual

Cache 6-21
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 6-5. Write-Once Protocol
WB/WT = 0
WB/WT = 1
WB/WT = 0
WB/WT = 0
Line Fill
System Bus
Other
Bus
Master
System
Logic
AMD-K5
Processor
Main
Memory
Look-Through
L2 Cache
1
WB/WT = 1
2
3
1
2
Writethrough
Writethrough
1
2
3

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm