6-20 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
The writethrough to memory must be accompanied by an
invalidation of this line in any other caching master’s cache.
3. During the second write to that line, the processor updates
its shared line and writes through to the exclusive line of the
L2 cache. At the same time system logic drives the L1 WB/
WT input High (writeback), the L2 WB/WT input can also
be driven but has no effect. This leaves the L1 and L2
caches as follows:
L1 cache line in the exclusive state
L2 cache line in the modified state
(If the design of the L2 permits line transitions directly
from the shared to modified state, the state transitions in
Step 2 can be skipped.)
4. During the next write to that line, the processor updates its
exclusive line. The WB/WT input has no effect. This leaves
the L1 and L2 caches as follows:
L1 cache line in the modified state
L2 cache line in the modified state
5. During all subsequent writes to that line, the processor sim-
ply updates its modified line.
Inquire cycles to the L2 cache that occur between Steps 1 and 3
get a HIT but not a HITM, thus avoiding the need to drive
simultaneous or subsequent inquire cycles to the L1 cache.
These inquire cycles to the L2 cache are done in parallel with
the processor’s L1 and L2 accesses, so they do not reduce the
processor’s performance when it works out of its caches. How-
ever, inquire cycles to the L2 cache that occur after Step 3 get
a HITM. In these cases, the L2 cache drives a subsequent
inquire cycle to the L1 cache, which may have updated a modi-
fied copy after the last update to the L2 cache. These inquire
cycles to L1 are done in parallel with the processor’s own L1
accesses, but they will block the processor’s access to the L2
cache.
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