6-10 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
writethroughs, which are driven as single writes rather than
burst writes.
From the system’s viewpoint, the cacheability of bus cycles is
controlled by the KEN and WB/WT inputs, as described in Sec-
tion 6.1.3 on page 6-4. During reads, system logic can use the
assertion of CACHE to initiate a table lookup of cacheable
addresses. Such lookups are not normally necessary during
writebacks, because the location (having already been cached)
is known to be cacheable and KEN has no effect on the proces-
sor during writes (only during reads).
The MESI state of a cache-line fill (read miss) or a write hit to a
shared line is determined by the states of the PWT bits and the
WB/WT input signal. The MESI-state transitions for reads and
writes are given in Table 2-2 on page 2-19. Complete descrip-
tions of the signals that control cacheability and cache coher-
ency are given on the following pages:
■ CACHE—Section 5.2.15 on page 5-49
■ EADS—Section 5.2.20 on page 5-58
■ HIT—Section 5.2.25 on page 5-70
■ HITM—Section 5.2.26 on page 5-72
■ INV—Section 5.2.33 on page 5-88
■ KEN—Section 5.2.34 on page 5-89
■ PCD—Section 5.2.39 on page 5-99
■ PWT—Section 5.2.43 on page 5-105
■ WB/WT—Section 5.2.56 on page 5-133
6.2.3 Writethrough vs. Writeback Coherency States
The terms writethrough and writeback apply to two related con-
cepts in a read/write cache like the processor’s L1 data cache
or an L2 cache. The following conditions apply to both the
writethrough and writeback modes:
■ Memory Writes—There is a relationship between memory
writes and their concurrence with cache updates:
• A memory write that occurs concurrently with a cache
update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
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